1. Field of Invention
The present invention generally relates to semiconductor processing and, more particularly, to a method of wet etching a dielectric material while exposing polysilicon.
2. Related Art
With increasing densities of up to hundreds of thousands of devices on a single chip, improper isolation among devices, such as flash memory devices, will cause current leakage, which can consume significant amounts of power. In addition, improper isolation between devices can damage the circuit temporarily or permanently. Still further, improper isolation can result in noise margin degradation, voltage shift, or crosstalk.
One isolation technique proposed for semiconductor chips with high integration is the trench isolation process, or the shallow trench isolation (STI) process. A trench region is formed in the semiconductor with a depth deep enough for isolating the devices or different wells. In general, a trench is etched and filled with insulating or dielectric materials, such as silicon dioxide. The insulating material is then etched to expose portions of the devices, many of which contain polysilicon.
Typically, a wet etchant has been used to etch the insulating material between the devices. A conventional wet etchant is hydrofluoric acid (HF) diluted with deionized water. Diluted HF has the advantage of dissolving silicon dioxide without attacking silicon, silicon nitride, or polysilicon. Problems encountered with the use of typical diluted HF solutions have included lack of etch penetration into small geometries related to shrinking trench widths and lifting of the photoresist in wet etch processes involving photoresist masks.
Another conventional wet etchant is a buffered oxide etchant (BOE) solution comprising HF mixed with ammonium fluoride (NH4F), deionized water, and a surfactant. A BOE solution is useful to provide a consistent etch rate due to the extra fluorine buffer. Problems encountered with the use of a typical BOE solution have included gate polysilicon loss concurrent with the etch of the insulating material.
Therefore, what is needed is a method to etch insulating material between highly integrated devices having very small geometries with minimal gate polysilicon loss. Further, etching insulating material between highly integrated devices with the aforementioned characteristics in conjunction with a photoresist is desirable when processing certain devices.
The present invention provides a method for forming two gate structures separated by a dielectric and wet etching the dielectric between the gate structures to expose at least a portion of the polysilicon layer of the gate structures with minimal polysilicon loss.
In one embodiment of the present invention, a method of etching a dielectric layer in the presence of polysilicon comprises forming two gate structures over a semiconductor substrate, each of the gate structures comprising a polysilicon layer, forming a trench between the two gate structures, depositing a dielectric layer between the two gate structures, and etching portions of the dielectric layer with a wet etch solution to expose polysilicon portions of the gate structures, the wet etch solution comprising surfactant and between about 0% and 10% by weight NH4F.
In another embodiment, a method of etching a dielectric layer in the presence of polysilicon comprises forming two gate structures over a semiconductor substrate, each of the gate structures comprising a polysilicon layer, forming a trench between the two gate structures, depositing a dielectric layer between the two gate structures, and etching portions of the dielectric layer with a wet etch solution to expose polysilicon portions of the gate structures, the wet etch solution comprising surfactant and between about 0% and 10% by weight NH4F, and the etching occurring with a dielectric-to-polysilicon selectivity above about 15.
In yet another embodiment of the present invention, a method of manufacturing a semiconductor device comprises forming a first region over a semiconductor substrate, the first region having at least two gate structures, and each of the at least two gate structures comprising a polysilicon layer, forming a second region over the semiconductor substrate, forming a trench between the at least two gate structures, depositing a dielectric layer between the at least two gate structures, forming a photoresist layer over the second region, and etching portions of the dielectric layer only in the first region with a wet etch solution to expose polysilicon portions of the at least two gate structures, the wet etch solution comprising between about 0% and 10% by weight NH4F.
Advantageously, the present invention provides a method for etching dielectric material between highly integrated polysilicon devices having small geometries with high dielectric-to-polysilicon selectivity to expose polysilicon with less polysilicon loss than was previously possible with conventional methods. Further, the present invention advantageously allows for highly selective wet etching in conjunction with photoresist without lifting of the resist.
This invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.